1. Field of the Invention
The invention in general relates to the field of integrated circuitry, and particularly, to a wafer scale circuit arrangement and the packaging therefore.
2. Background Information
In wafer scale integration, all of the electronic circuitry normally used in a given system or device may be fabricated on a large single monolithic semiconductor wafer. Wafer scale integration can potentially replace integrated circuit chips, circuit boards, and a multitude of interconnecting wires, thereby resulting in faster operating and more reliable apparatus.
Wafer scale integrated circuit devices have the potential for accommodating millions of electronic functions and therefore the inputting and outputting of signals is an important design consideration. Additionally, with millions of functions being performed on the single wafer, some wafers may generate hundreds or even thousands of watts of heat and accordingly heat removal is a primary consideration in the design of an apparatus using one or more wafer scale integrated circuits.
The present invention provides an economical packaging approach for assembly of complete devices or systems such as data and signal processors, using full silicon wafers.